System-level Approaches to Power Efficiency in FPGA-based Designs (Data Reduction Algorithms Case Study)

Abstract

 This study presents first findings from a system-level investigation of FPGA-based systems' power efficiency.
 Sophisticated systems (such embedded sensor nodes) may be implemented thanks to advanced FPGA chips. It
 makes sense to move the design process to higher abstraction layers, or system-levels of design, since creating
 such sophisticated applications is unaffordable at lower levels. At these higher abstractions, our work
 demonstrates that at least a certain degree of power awareness is possible. A approach for a power-aware,
 system-level algorithm paritioning is described, along with first findings. Due to the significance of data
 reduction methods in wireless sensor networks (WSNs), we have chosen them as the case study. The given
 concepts are expected to be applicable to various untethered embedded systems based on FPGAs and other
 comparable programmable devices, even if the study has been concentrated on WSN applications of FPGA